In the following circuit, the output Y for all possible inputs A and B is expressed by the truth table

1. A. array ccc A & B & Y 0 & 0 & 1 0 & 1 & 1 1 & 0 & 1 1 & 1 & 0 array
2. B. array ccc A & B & Y 0 & 0 & 1 0 & 1 & 0 1 & 0 & 0 1 & 1 & 0 array
3. C. array ccc A & B & Y 0 & 0 & 0 0 & 1 & 1 1 & 0 & 1 1 & 1 & 1 array
4. D. array ccc A & B & Y 0 & 0 & 0 0 & 1 & 0 1 & 0 & 0 1 & 1 & 1 array

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