Logic Gates Logic Gates Logic Gates Truth Tables Gate Symbol Boolean Expression Output High Condition Truth Table Summary AND needs All, OR needs One, NOT flips the bit, and bubbles (NAND/NOR) simply invert the Basic gate result. AND Gate Solid D-shape Y = A B Both inputs are 1 (0,0) 0; (0,1) 0; (1,0) 0; (1,1) 1 OR Gate Curved input side, pointed output Y = A + B At least one input is 1 (0,0) 0; (0,1) 1; (1,0) 1; (1,1) 1 NOT Gate Triangle with small circle (Inverter) Y = A Input is 0 (0) 1; (1) 0 NAND Gate AND gate with bubble at output Y = A B At least one input is 0 (0,0) 1; (0,1) 1; (1,0) 1; (1,1) 0 NOR Gate OR gate with bubble at output Y = A + B Both inputs are 0 (0,0) 1; (0,1) 0; (1,0) 0; (1,1) 0 XOR Gate OR gate with additional curved line at input Y = A B = A B + A B Inputs are different ( 0,1 or 1,0 ) (0,0) 0; (0,1) 1; (1,0) 1; (1,1) 0 logic gates truth tables Digital electronics works with two stable states: logic 0 (LOW) and logic 1 (HIGH). A logic gate is a small decision-maker: it looks at one or more inputs (each either 0 or 1) and produces a single output (0 or 1) according to a rule. These rules come from Boolean algebra, where addition corresponds to OR, multiplication corresponds to AND, and inversion (bar) corresponds to NOT. You already experience logic daily: a room light controlled by two switches is a practical OR or XOR; an appliance that works only when both the plug is inserted and the power is ON is an AND. Because 0/1 can be represented by low/high voltages in simple circuits, gates can be built from diodes and transistors. For NEET, you must recognise the standard symbols, write/read their truth tables, translate between symbols and Boolean expressions, and implement any gate using only NAND or only NOR (called universal gates). With this skill, you can quickly predict outputs, simplify expressions using identities (like De Morgan’s laws), and spot typical traps such as double inversion or floating inputs. We adopt the usual Boolean notation: + for OR, (or adjacency) for AND, and an overbar for NOT. We consider two-input gates unless stated. Inputs and outputs are dimensionless logic states; in hardware these are voltage levels (e.g., near 0 V = 0, near V CC = 1) with noise margins so small disturbances do not flip logic. The heart of many exam problems is converting a small logic network into a Boolean expression, simplifying it, and evaluating for specific inputs. You will also learn how NAND and NOR alone can generate NOT, AND, OR, and more complex functions, which lets you redesign or mentally simulate circuits under time pressure. Real-world picture: Think of water taps. OR gate: water flows if tap A or tap B is open. AND gate: water flows only if both taps are open. NOT gate: an automatic valve that closes when a sensor is active (inverts the sensor’s logic). remember The digital state of a signal: 0 (LOW) or 1 (HIGH). Represented by voltages near 0 V and near the supply voltage. Logic level A variable that can take only two values: 0 or 1. Shown by letters like A, B, X, Y in logic circuits. Boolean variable A complete listing of outputs for all possible input combinations of a logic function. Truth table Universal gate A gate type that can implement any Boolean function by itself. NAND and NOR are universal. Key identities: A + B = A , , B and A B = A + B . De Morgan’s laws A small circle on a gate symbol indicating logical inversion (NOT) at that input or output. Inversion bubble Number of inputs a gate can accept (e.g., 2-input OR, 3-input AND). Fan-in Number of gate inputs that one output can drive reliably without violating logic levels. Fan-out Propagation delay Time taken by a gate’s output to respond after the inputs change. The allowed disturbance in voltage levels so that logic 0/1 is still interpreted correctly. Noise margin Output is 1 when any input is 1. OR gate (two-input) Used in digital electronics and Boolean algebra to determine the output state (Y) when at least one of the two binary inputs (A or B) is act AND gate (two-input) Output is 1 only when all inputs are 1. This formula governs the operation of a two-input digital logic gate, determining that the output is true only if all inputs are true. Output is the complement of the input. NOT gate (inverter) Applies to digital logic circuits (inverters) where the output signal is the logical inverse of the input signal. Output is 1 when inputs are different. XOR gate (two-input) Used in digital electronics to determine an output (Y) that is true (1) if and only if the two inputs (A and B) are different. XNOR gate (two-input) Output is 1 when inputs are the same. This expression defines the output (Y) of an XNOR gate, which is true (1) only when both inputs (A and B) are equal. Compute logical AND of inputs. This is 1 only if both A and B are 1. Invert the AND result. This makes output 0 only when both A and B are 1; otherwise it is 1. Y = A B ( NAND gate ) Inputs A and B are binary (0 or 1). Complement operation follows Boolean algebra rules. Independent of physical implementation (ideal logic). Y = A B Y = A + B ( NOR gate ) Inputs are binary. Ideal inversion and ideal OR operation. Y = A + B Compute logical OR of inputs. This is 1 if any one of A, B is 1. Invert the OR result. This yields 1 only when both A and B are 0. NAND is NOT of AND: output is LOW only when all inputs are HIGH. NOR is NOT of OR: output is HIGH only when all inputs are LOW. OR gate: The output becomes HIGH if at least one input is HIGH. In Boolean language Y = A + B . It mirrors everyday decisions like “I will go if it is Saturday OR Sunday.” The truth table has a single 0 case (A = 0, B = 0). In circuit symbols, OR has a curved input side. Be careful: + here is not arithmetic addition; it is logical addition capped at 1. AND gate: Output is HIGH only if all inputs are HIGH. In Boolean form Y = AB (or A B ). Analogy: “You can unlock the door only if you have the key AND you enter the correct code.” Its truth table has three 0s and one 1. This maps to series constraints in real life: both conditions must be satisfied together. NOT gate (inverter): Flips the input, so Y = A . Symbol: a triangle with an inversion bubble. In algebra, the overbar means complement: 0 = 1 , 1 = 0 . Two NOT gates in series cancel: A = A . This simple idea powers many reductions in logic networks. NAND gate: “NOT-AND.” Since Y = AB , its output is 0 only for A = 1, B = 1. Otherwise it is 1. NAND is a universal gate: any logic function can be made using only NANDs. For example, connect both inputs of a NAND to the same signal A: Y = A A = A , which is a NOT. NOR gate: “NOT-OR.” With Y = A + B , its output is 1 only when both inputs are 0. NOR is also universal. Similar trick yields a NOT: short both inputs to A, then Y = A + A = A . Universal gates are prized in hardware because a single type of chip can implement many functions. XOR gate (exclusive OR): Y = A B = A B + A B . It acts like “either A or B, but not both.” XOR is common in parity checks and adders. It is not universal by itself. XNOR produces 1 if inputs are equal: Y = AB + A , B . These two are complementary: A B = XNOR (A,B) . OR (A+B) AND (A·B) NAND (¯(AB)) NOR (¯(A+B)) Overbar shown as ¯ for readability; algebraically: NAND = AB , NOR = A+B . XOR (A⊕B) XNOR (¯(A⊕B)) tip Boundary conditions: For OR, only (0,0) gives 0. For AND, only (1,1) gives 1. This one-line memory helps reconstruct the entire table quickly. Reading symbols quickly: Look for inversion bubbles to spot hidden NOTs. A bubble at the output means the whole function is inverted. Bubbles on inputs often indicate a De Morgan transform: an AND gate with bubbles on all inputs is equivalent to a NOR without bubbles at inputs (and vice versa). NOT: Tie both inputs of a NAND to A → Y = AA = A . AND: First NAND the inputs, then NAND the result with itself → Y = AB , AB = AB . OR: NAND each input with itself (two NOTs), then NAND those results → Y = A , B = A + B (by De Morgan). Build basic gates from NAND (universal) NOT: Tie both inputs of a NOR to A → Y = A + A = A . OR: First NOR the inputs, then NOR the result with itself → Y = A + B + A + B = A + B . AND: NOR each input with itself (NOTs), then NOR those → Y = A + B = AB (De Morgan). Build basic gates from NOR (universal) De Morgan in practice: If an entire block is inverted, you can push the inversion to each input by flipping the gate: A + B = A , B but with an AND (gate changes), and AB = A + B but with an OR. Visually, move the output bubble to inputs and switch the gate type. Boolean identities you will actually use: (i) Idempotent: A + A = A , AA = A . (ii) Null: A + 1 = 1 , A 0 = 0 . (iii) Identity: A + 0 = A , A 1 = A . (iv) Complement: A + A = 1 , A A = 0 . (v) Double negation: A = A . (vi) Commutative and associative for + and . Simplification strategy: Translate the circuit into Y( inputs ) , then cancel using idempotent and complement laws. If you see a full overbar over a sum or product, consider De Morgan immediately. Spotting X + X Y = X + Y -type absorptions is a time saver. Always check if you can factor terms to expose a complement pair. Multiple-input gates: A 3-input OR has Y = A + B + C and is 1 unless all are 0. A 3-input AND has Y = ABC and is 1 only if all are 1. NAND/NOR generalise similarly: Y = ABC and Y = A + B + C . In tables, there are 2 n rows for n inputs. Voltage picture (qualitative): Logic 0 is a small voltage (near 0 V), logic 1 is near the supply (e.g., 5 V). Real gates ensure noise margins so small fluctuations do not cause misinterpretation. Inputs must never be left floating; a floating input can randomly be sensed as 0 or 1 and can also pick up noise. neet-alert NEET trap: A bubble at the input flips that input before the gate acts. An AND with both inputs bubbled is equivalent to an OR without bubbles at inputs, but with a bubbled output (NOR). Track bubbles carefully. neet-alert NEET trap: XOR is not the same as OR. OR is 1 for (1,1), but XOR is 0 for (1,1). If you forget this, half-adder and parity questions go wrong. XOR constructions: Using only NANDs, one realisation is Y = (A , NAND ,B) , NAND ,((A , NAND ,(A , NAND ,B)) , NAND ,(B , NAND ,(A , NAND ,B))) . In exams, you rarely need internal structure; instead, know the compact form A B = A B + A B to compute outputs fast. XNOR quick test: If inputs are equal, XNOR = 1. This makes XNOR a useful equality detector. For n inputs, an even-parity detector is a chain of XORs; its complement is odd parity. Such ideas may appear qualitatively in matching questions. Reading a small logic network: Work from inputs to output. Replace each gate by its Boolean operation, keep careful parentheses, and simplify after each stage. If a gate’s output is inverted, place a bar over the entire subexpression from that gate. Speed considerations (qualitative): Each gate adds propagation delay. A deep chain of gates is slower than a shallow one. When two designs are logically equivalent, fewer levels of logic are usually preferred. Fan-out limits also restrict how many inputs a single output can reliably drive. Input conventions: If an input has a bubble on the symbol pin (called active-LOW input), it means the gate expects a 0 to be interpreted as asserted. For analysis, treat the bubble as an inverter attached to that input. Redraw the circuit without bubbles if that is clearer. Common mental checks: (i) For OR family (OR, NOR), the all-zero row is special. (ii) For AND family (AND, NAND), the all-one row is special. (iii) For XOR family, the diagonal rows (0,1) and (1,0) decide the 1s. Use these patterns to sanity-check any truth table under exam pressure. From truth table to expression: Sum-of-products (SOP) form lists a product term for each row where output is 1, then ORs them. Product-of-sums (POS) lists a sum term for each 0-output row, then ANDs them. Minimisation compresses SOP/POS using identities. For NEET, light algebraic simplification is enough. Design using universals: If only NAND gates are allowed, replace every OR by its NAND equivalent using De Morgan, and every NOT by a NAND tied to itself. Similarly for NOR-only designs. Count gates and levels; if two designs are possible, choose the one with fewer levels to reduce delay. Edge cases to watch: Double inversion ( X =X ) might be hidden across two bubbles. Also, sometimes the same subexpression appears twice; idempotence lets you drop duplicates ( X+X=X , XX=X ). If an input is both a variable and its complement in the same product, that product is 0. Practical note (qualitative only): TTL and CMOS families define exact voltage ranges for logic 0 and 1. You are not required to memorise those for NEET, but you should know the idea of noise margin: a buffer zone that prevents small noise from flipping the interpreted logic state. Only-NAND world: First make NOT, then AND, then OR. Only-NOR world: First make NOT, then OR, then AND. Think “NOT first, then family gate.” NAND gives 1 only when both inputs are 1. That is AND. NAND is the inverted AND, so it gives 0 only when both inputs are 1; otherwise it gives 1. XOR and OR are the same because both turn on when any input is 1. XOR is 0 at (1,1); OR is 1 at (1,1). XOR is “odd-ones detector” for two inputs. A bubble at the input means output is simply inverted. A bubble at input inverts that input only. The gate then processes the inverted input normally. Only a bubble at the output inverts the whole gate’s result. OR is 1 if any input is 1. AND requires both 1s. Invert the AND result. Y OR, Y AND, Y NAND Foundation check dimensionless (logic levels) Use Y OR = A + B , Y AND = AB , Y NAND = AB . Easy: Write the truth table and outputs for OR, AND, NAND for inputs A=1, B=0. easy A = 1 B = 0 NOT A from NAND. NOT B from NAND. De Morgan converts NAND of complements to OR. dimensionless Universal gates NAND-only expression for OR Medium: Implement OR using only NAND gates. Give the Boolean proof. Make NOT using NAND, then apply De Morgan. Available gate: NAND only Need: Y = A + B medium dimensionless Algebraic simplification Simplified Y and a NOR-only construction sketch De Morgan to split the overbar of a product. Double inversion cancellation. Absorption: (X + XY) = X , with X = A + B , Y = B . Y = A + B , , A , B hard Hard: Simplify Y = A + B , , A , B and state an all-NOR implementation plan. Use De Morgan, idempotent, and complement laws. Boundary check habit: Substitute A=0,B=0 and A=1,B=1; if a claimed identity fails on these corners, it is wrong. Quick corner checks save time. tip Worked mental example: For the network (A and B) feeding a bubble (NAND), followed by another bubble (NOT), the two inversions cancel: AB = AB . Spotting paired inversions turns a scary symbol chain into a simple AND. Design thought: When restricted to NANDs, try to rewrite the final expression in terms of only complements of sums or products that match NAND patterns. Similarly, with NOR-only design, favour expressions where an overall overbar covers sums. This alignment reduces the number of extra inverters you need. On SOP and POS forms: If a function has only a few 1s in its truth table, SOP may be shorter. If it has only a few 0s, POS may be shorter. Although Karnaugh maps are beyond scope here, this intuition helps you choose the faster algebraic path. Equivalence spotting: An AND with inverted inputs followed by an output bubble is a NOR. Dually, an OR with inverted inputs followed by an output bubble is a NAND. These symbol dualities compress circuit reading time dramatically. Functional completeness intuition: Because NAND gives you NOT and, via a pair of NANDs, AND and OR, any combination of AND/OR/NOT can be built. Since AND/OR/NOT generate all Boolean functions, NAND alone is sufficient. The same logic proves NOR’s completeness. Half-adder hint (qualitative): Sum = A B , Carry = AB . So if a question gives Sum and Carry truth values for some bits, you can back-infer A and B pairs by matching XOR and AND rows. Keep in mind: XOR is 1 for different inputs. Don’t float inputs: In practice, an unconnected input can randomly read as 0 or 1 due to stray capacitance or interference. In logic analysis, if an input is unspecified, treat it as a variable; do not assume it is 0. If a problem states “unused inputs are tied LOW,” then and only then take them as 0. Three quick Boolean moves you should automatise: (1) Cancel double bars; (2) Apply absorption ( X + XY = X , X(X + Y) = X ); (3) Use complement pairs to drop terms ( X + X Y = X + Y ). These reduce expressions in two or three steps during the exam. Check with corner pairs: If your simplified result is an OR-like expression, verify that (0,0) gives 0 and (1,1) gives 1. If it fails, you likely dropped a complement wrongly or misapplied De Morgan. Consistency checks prevent last-minute blunders. Chain of XORs: A B C is 1 when an odd number of inputs are 1. Parentheses do not matter due to associativity of XOR. If a question hides XOR as A B + A B , you can extend it by substituting ( ) C and expanding similarly. Contrast NAND vs NOR at a glance: NAND is mostly 1s with a single 0 at (1,1). NOR is mostly 0s with a single 1 at (0,0). Memorising these “corner rows” speeds up your truth table writing when options are close. Output dominance patterns: For OR, a single 1 dominates to make output 1; for AND, a single 0 dominates to make output 0. In elimination questions, look for the presence of a dominating input that fixes the output regardless of the other input state. Complement trick with factors: If you see AB + AC , factor as A(B + C) = A , + (B + C) ? Careful: By De Morgan, A(B + C) = A + (B + C) = A + ( B , C ) . Track each bar and parenthesis. Equating forms: If a problem asks whether two circuits are equivalent, derive both Boolean expressions, simplify independently, and compare. If they match algebraically (or via truth tables), the circuits are equivalent. Do not rely only on visual similarity of symbols. Minimal gate count heuristic: Prefer sharing subexpressions rather than recomputing them; prefer using bubbles strategically to avoid extra explicit NOT gates; and match your target technology (NAND-only or NOR-only) to cut down redundant conversions. Interpreting active-LOW outputs: If the output pin has a bubble, the function provided is the complement of the named function. For example, a gate labeled “AND” but drawn with a bubbled output is actually a NAND. Translate names to algebra before computing results. Big picture: All logic reduces to combinations of OR, AND, and NOT. NAND and NOR are just compact ways to bundle AND/OR with NOT. Master the identities, and every small logic puzzle becomes a short, mechanical simplification. remember OR Logical addition: Y = A + B ; 1 if any input is 1. AND Logical multiplication: Y = AB ; 1 only if all inputs are 1. Inversion: Y = A ; flips 0↔1. bar NOT NAND NAND NOT-AND: Y = AB ; universal gate. NOR NOT-OR: Y = A + B ; universal gate. NOR XOR Exclusive OR: Y = A B = A B + A B ; 1 for different inputs. Complement of XOR: Y = AB + A , B ; 1 for equal inputs. XNOR Universal gate Gate type that can implement any function by itself (NAND, NOR). A + B = A , B ; AB = A + B . De Morgan’s laws Key terms recap